Akiko Specification

Akiko Specification

Akiko functions as the main control gate array for the Amiga CD32 Game System (CDGS). It acts as an interface between the processor and the custom chips buffering the data and generating the control signals. It also contains an interface for talking to a CD drive mechanism and a corner turn memory for accelerating Chunky to Planar pixel conversion. This device occupies position U5 in the CD game system.

Configuration

This device is configured as a 160-pin plastic quad flat pack (PQFP) package, with external dimensions as shown in Figure 4-2.

Pinout

I «

Input

0 =

Output

B =

Bidirectional

P =

Power

PIN«

NAME

TYPE

Description

1

VDDE1

P

Power

2

PD16

B

Processor Data

3

PD17

B

Processor Data

4

PD18

B

Processor Data

5

PD19

B

Processor Data

6

PD20

B

Processor Data

7

PD21

B

Processor Data

8

PD22

B

Processor Data

9

PD23

B

Processor Data

10

VSSE4

P

Power

11

PD24

B

Processor Data -

12

PD25

B

Processor Data

13

PD26

B

Processor Data

14

PD27

B

Processor Data

15

PD28

B

Processor Data

16

PD29

B

Processor Data

17

PD30

B

Processor Data

18

PD31

B

Processor Data

19

VDDE3

P

Power

20

CDO

B

Custom Chip Data

21

CD16

B

Custom Chip Data

22

CD1

B

Custom Chip Data

23

CD17

B

Custom Chip Data

24

CD2

B

Custom Chip Data

25

CD18

B

Custom Chip Data

26

CD3

B

Custom Chip Data

27

CD19

B

Custom Chip Data

28

CD4

B

Custom Chip Data

29

CD20

B

Custom Chip Data

30

VSSE5

P

Power

31

CDS

B

Custom Chip Data

32

CD21

B

Custom Chip Data

33

CD6

B

Custom Chip Data

34

CD22

B

Custom Chip Data

35

CD7

B

Custom Chip Data

36

CD23

B

Custom Chip Data

37

CDS

B

Custom Chip Data

38

CD24

B

Custom Chip Data

39

CD9

B

Custom Chip Data

40

CD25

B

Custom Chip Data

41

VSS11

P

Power

42

CD10

B

Custom Chip Data

43

CD26

B

Custom Chip Data

44

VSSE1

P

Power

45

CD11

B

Custom Chip Data

46

CD27

B

Custom Chip Data

47

CD12

B

Custom Chip Data

48

CD28

B

Custom Chip Data

49

CD13

B

Custom Chip Data

50

CD29

B

Custom Chip Data

51

CD14

B

Custom Chip Data

52

CD30

B

Custom Chip Data

53

CD15

B

Custom Chip Data

54

CD31

B

Custom Chip Data

55

VDD13

P

Power

56

RAS

I

Processor Reset

57

AWE

I

Alice Write Enable

58

SCANEN

I

Test Mode Enable

59

BCLK

I

CD Bit Clock

60

VSSE3

P

Power

61

CPUCLK

I

CPU Clock

62

VSSSS3

P

Power

63

BCAS0

0

Buffered Cas Byte 0

64

BCAS1

0

Buffered Cas Byte 1

65

CAS

I

Buffered Cas Byte from Alice

66

BCAS2

0

Buffered Cas Byte 2

67

BCAS3

0

Buffered Cas Byte 3

68

ADRAO

I

DRAM Address 0 from Alice

69

ADRA1

I

DRAM Address 1 from Alice

70

RDRAO

I

DRAM Address 0 to DRAM

71

RAMEN

0

RAM Enable/Chip Memory Access

72

REGEN

0

Register Enable/Chip Register Access

 

 

 

PIN # (con't)

NAME (cont)

TYPE (cont)

Signal Description (con't)

73

ROMEN

0

ROM Enable

74

DBR

1

Chip Data Bus Request

75

RWE..

0

DRAM Write Enable

76

IFCLK

1

CD Command Interface Clock

77

IFDAT

B

CD Command Interface Data

78

IFD1R

1

CD Command Interface Direction

79

LRCLK

1

CD Data Loft/Right Clock

80

VDD12

P

Power

81

VDDE2

P

Power

82

DATA

1

CD-Data Data

83

C2PO

1

CD-Data Errors

84

1NT2

0

Interrupt Request (Chips)

85

INT3

I

Interrupt Request (Chips)

86

INT6

0

Interrupt Request (Chips)

87

BLS

0

Blitter Slow Down

88

SCOR

1

CD-Subcode Sync

89

SUBCL

0

CD-Subcode Clock

90

SUBDAT

1

CD-Subcode Data

91

WFCLK

1

CD-Subcode Frame Clock

92

LED

B

Power On LED / Audio Filter Disable

93

MUTE

B

Audio Mute Signal

94

VSSE8

P

Power

95

FIREO

B

F«re Button

96

FIRE1

B

Fire Button

97

KBCLK

B

Keyboard Clock (Keyboard)

98

KBDATA

B

Keyboard Data (Keyboard)

99

IOPO

B

General Purpose I/O Pin 0

100

IOP1

B

General Purpose I/O Pin 1

101

BR

0

Bus Request

102

BG

1

Bus Grant

103

VDDE5

P

Power

104

BERR

0

Bus Errors

105

AS

B

Address Strobe

106

DS

B

Data Strobe

107

RW

B

Processor Read/Write

108

SZO

B

Data Transfer Size

109

SZ1

B

Data Transfer Size

110

DSACKO

B

Data Transfer Termination

111

DSACK1

B

Data Transfer Termination

 

 

PIN # (cont)

NAME (cont)

TYPE (cont)

Signal Description (con't)

112

VSSE2

P

Power

113

A23

B

Processor Address Bus

114

A22

B

Processor Address Bus

115

A21

B

Processor Address Bus

116

A20

B

Processor Address Bus

117

A19

B

Processor Address Bus

118

A18

B

Processor Address Bus

119

A17

B

Processor Address Bus

120

A16

B

Processor Address Bus

121

VSS12

P

Power

122

EXTACC

1

Processor Address Bus

123

A15

B

Processor Address Bus

124

A14

B

Processor Address Bus

125

A13

B

Processor Address Bus

126

A12

B

Processor Address Bus

127

A11

B

Processor Address Bus

128

A10

B

Processor Address Bus

129

A9

B

Processor Address Bus

130

AS

B

Processor Address Bus

131

VSSE7

P

Power

132

A7

B

Processor Address Bus

133

A6

B

Processor Address Bus

134

A5

B

Processor Address Bus

135

A4

B

Processor Address Bus

136

A3

B

Processor Address Bus

137

A2

B

Processor Address Bus

138

A1

B

Processor Address Bus

139

A0

B

Processor Address Bus

140

VDDE4

P

Power

141

PDO

B

Processor Data

142

PD1

B

Processor Data

143

PD2

B

Processor Data

144

PD3

B

Processor Data

145

PD4

B

Processor Data

146

PD5

B

Processor Data

147

PD6

B

Processor Data

148

PD7

B

Processor Data

149

VSSE6

P

Power

150

PD8

B

Processor Data

 

 

PIN « (con't)

NAME (con't)

TYPE (cont)

Signal Description (con't)

151

PD9

B

Processor Data

152

PD10

B

Processor Data

153

PD11

B

Processor Data

154

PD12

B

Processor Data

155

PD13

B

Processor Data

156

PD14

B

Processor Data

157

PD15

B

Processor Data

158

cpll

1

CPU Space Cycle (F.P.U)

159

RESET

B

General Reset

160

VDD12

P

Power